1. Which among the bipolar logic families ¡s specifically adopted for high-speed applications?
a)
Diode Transistor Logic (DTL)
b)
Transistor Transistor Logic (TTL)
c) Emitter Coupled Logic (ECL)
d)
Integrated Injection Logic (12l)
2.
Which type of unipolar logic family exhibits its
usability for applications requiring low power consumption?
a)
PMOS
b)
NMOS
c) CMOS
d)
All of the above
3.
Which type of output current flows towards or
into the output terminal in a logic circuit?
a)
Sourcing current
b) Sinking current
c)
Both a and b
d)
None of the above
4.
Suppose that the digital IC family has a fan out
of 6. It implies that the gate can supply the current to of same family.
a) 6 inputs
b)
6 outputs
c)
12 nodes
d)
12 branches
5.
What does the below stated OR Law imply, while performing
OR operation of an input with ‘1’? Expression of OR Law: A+ 1 = 1
a)
Output will always be equal to input
b) Output will always be high
c)
Output will always be low
d)
Output will always be same
6.
How is the relation specified between ¡n put and
output in logic circuits?
a)
Switching equations
b)
Truth-table
c)
Logic diagram
d) All of the above
7.
Which is an incorrect rule of binary subtraction
from the following?
a)
0 - 0 = 0
b) 0 - 1 = -1
c)
1 - 0 = 1
d)
0 - 1 = 1 with borrow ’1’
8.
What should be the output of converter, if a
common anode display segment ¡s to be turned ‘ON’?
a) ‘O’
b)
‘1’
c)
Both a and b
d)
None of the above
9.
Which adder plays a crucial role in eliminating
the problem associated with the inter-stage carry delay?
a)
Half adder
b)
full adder
c)
BCD adder
d) Look-a head carry adder
10.
Which among the following is/are responsible for
the occurrence of clock skew by introducing delays from different paths of
clock generator to various circuits?
a)
Different length of wires
b)
Gates on the paths
c)
Gating of clock to control the loading of
registers
d) All of the above
11.
Which ¡s the prohibited state/ condition in S-R
latch and needs to be avoided due to unpredictable nature of output?
a)
S = R = O
b)
S = O, R = 1
c)
S = 1, R = O
d) S = R = 1
12.
What does the data in parallel form of
representation in registers, known as?
a)
Temporal Code
b)
Spectral Code
c) Special Code
d)
Factorial Code
13.
Which type of triggering is shown by the D flip
flops in buffer registers for the temporary storage of digital words?
a)
Positive level triggering
b)
Negative level triggering
c)
Positive edge triggering
d) Negative edge triggering
14.
When the mode control pin is connected to
ground, Universal Shift Register acts as ________
a)
Unidirectional register
b) Bidirectional register
c)
Multi-directional register
d)
None of the above
15.
The output of Up counters goes on increasing due
to
a)
Transmission of clock pulses
b) Reception of clock pulses
c)
Both a and b
d)
None of the above
16.
If the number of states in a counter are 2n,
then the value of ‘n’ ¡s __________
a)
Less than the number of flip flops
b)
Greater than the number of flip flops
c) Equal to the number of flip flops
d)
Unpredictable
17.
Which sequential circuits are applicable for
counting pulses?
a) Counters
b)
Flip Flops
c)
Registers
d)
Latches
18.
Which type of triggering phenomenon is exhibited
by Counters?
a) Edge
b)
Level
c)
Pulse
d)
All of the above
19.
Where do/does the status of memory element in a synchronous
sequential circuit get/s affected due to change in input?
a)
At an active edge of clock
b)
At passive edge of clock
c)
Both a and b
d)
None of the above
20.
Which type of memory elements are used ¡n
synchronous sequential circuits?
a) Clocked Flip flops
b)
Unclocked Flip flops
c)
Time Delay Elements
d)
All of the above
21.
According to Moore circuit, the output of
synchronous sequential circuit depend/s on ______ of flip flop
a)
Past state
b) Present state
c)
Next state
d)
External inputs
22.
Which among the following are used in
programming array logic (PAL) for reducing the loading on inputs?
a) Input buffers
b)
Output buffers
c)
OR matrix
d)
AND matrix
23.
If the number of nichrome fuse links in PAL are
equal to 2M xn, then what does ‘n’ represent in it?
a)
Number of inputs
b)
Number of arrays
c)
Number of outputs
d) Number of product terms
24.
Which gates are used on the output side as
buffers in order to provide a programmable output polarity in PAL 16 P8 devices?
a)
AND
b)
OR
c) EX-OR
d)
NAND
25.
How many logic gates can be implemented in the
circuit by complex programmable logic devices (CPLDs)?
a)
10
b)
100
c)
1000
d) 10000
26.
Which bus ¡s used as input data bus by the
control lines for a specific duration while performing write operation?
a)
Uni directional bus
b)
Bi-directional bus
c)
Multi- directional
d)
None of the above
27.
Which operations are executed by the control
line at logic ‘1’ level?
a) Read
b)
Write
c)
Store
d)
All of the above
28.
Which among the following is/are a/the major disadvantage/s
of dynamic memory in shift registers?
a)
Less power consumption
b)
High packaging density
c) Necessity of additional circuitry for time
to time refreshing
d)
All of the above
29.
Which among the following memories utilizes the electrical
voltage for erasing purposes?
a)
PROM
b) EAROM
c)
RAM
d)
CAM
30.
The ability of HDL to describe the performance specification
of a circuit is regarded as ____
a)
Test case
b)
System case
c)
Mark bench
d) Test bench
31.
Which among the following is the correct way of
declaring the standard library in VHDL?
a)
std.standard_all
b)
std_standard.all
c)
standard_std_all
d) std.standard.all
32.
Which mode in VHDL allows to make the signal assignments
to a port of mode out by preventing it from reading?
a)
ln
b)
Out
c) In out
d)
Buffer
33.
From where do the voltage noise get induced into
the logic circuit?
a)
From a gate output to load
b)
From the connecting wires used between two gates
c) Both a and b
d)
None of the above
34.
If a high logic output drives a logic circuit
input, which among the below specified reasons will be responsible in causing a
voltage drop into an invalid state?
a)
Positive noise spike greater than VNL
b)
Positive noise spike less than VNL
c) Negative noise spike greater than VNH
d)
Negative noise spike less than VNH
35.
What should be the value of ¡n put voltage for
an efficient operation of a logic circuit by avoiding the conditions of invalid
voltage levels?
a)
Lower than VIL (max)
b)
Higher than VIH (mm)
c) Both a and b
d)
None of the above
36.
Which code is used for labeling the cells of
K-map?
a)
Binary
b) Gray
c)
BCD
d)
ASCII
37.
Which number? Code is added to an incorrect result
obtained ¡n BCD addition for correction purpose?
a)
One (0001)
b)
Three (0011)
c) Six (0110)
d)
Nine (1001)
38.
In delay flip-flop, after the propagation delay.
a)
Input follows ¡n put
b)
In put follows output
c) Output follows input
d)
Output follows output